Overview:
Timing engineering change orders (ECOs) between implementation and signoff tools can adversely impact your tapeout schedule. Traditional ECO flows lack physical context when coming up with fixes, which could lead to timing convergence issues and unpredictable time to signal integrity (SI) closure. Signoff driven closure in IC Compiler is an exact link to PrimeTimeSI and Star-RCXT to drive the final stages of SI closure. It uses incremental extraction and static timing analysis (STA) to drive powerful optimizations for a predictable time to SI closure.
This webinar is the first of a series highlighting key IC Compiler technologies speeding design closure. Up-coming topics include placement-congestion minimization, power-rail design and in-design physical verification.
Join our experts to learn how signoff driven closure combines signoff accuracy with powerful optimizations to accelerate your time to SI closure. You will get an overview of the technology, including its usage model and how it can be applied in an SI closure flow. You will learn about the analysis, optimization and interactive capabilities and see results illustrating its benefits.
Products Featured:
IC Compiler
Star-RCXT
PrimeTime SI
Who Should Attend:
- Place and Route design engineers
- Engineering managers
Select 'Register' to attend this event or click here for more information on Synopsys IC Compiler 2009 Webinar Series
Moderator:
 Clive "Max" Maxfield has now spent over a quarter of a century in the electronic, computing, and EDA arenas. In 1980, after obtaining his BSc in Control Engineering (an interesting mixture of math, electronics, mechanics, and hydraulics and fluids), Max joined a design team at International Computers Limited (ICL) creating CPUs for mainframe computers. In addition to designing ASICs and circuit boards, Max has written numerous test programs for functional and in-circuit testers. In the area of digital logic simulation, Max has created models of everything from ASIC cell libraries to microprocessors. Due to his digital expertise, Max was once appointed analog marketing manager at a large EDA company (the world is a funny old place sometimes).
In the early 1990s, Max thought it would be fun to see a book he'd written on the shelves in his local book store, so he penned his first tome Bebop to the Boolean Boogie (An Unconventional Guide to Electronics). Since that time, Max has authored and co-authored a number of books, including EDA: Where Electronics Begins, The Design Warrior's Guide to FPGAs, and How Computers Do Math (Featuring the Virtual DIY Calculator).
Presenters:
 Dr. Henry Sheng
Dr. Henry Sheng is R&D Group Director for Design Closure in IC Compiler. Henry and his organization are responsible for implementation extraction, timing and signal integrity, as well as Multi-corner Multi-mode (MCMM) and post-route closure. He has been with Synopsys since 1996. Henry holds a Ph.D. degree in Electrical Engineering and Computer Science from the University of California, Berkeley.
 Dr. Jinan Lou
Dr. Jinan Lou received his B.S. degree in Computer Engineering and Computer Science, M.S. and Ph.D. degrees in Computer Engineering, from University of Southern California, Los Angeles, in 1993, 1995 and 1999, respectively. He is currently a Principal Engineer at Synopsys. His research interests include physical optimization, layout driven logic synthesis and post-layout optimization for deep-submicron technologies.
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