Overview:
As networking in the home continues to integrate more devices requiring higher bandwidth, new generations of Ethernet designs are being incorporated into complex SoC subsystems. These bandwidth requirements are causing designers to rapidly migrate from Fast Ethernet to Gigabit Ethernet. To support these designs, a configurable and robust IP solution is needed to easily support the rapidly changing market demands.
In this webinar:
Learn how to accurately calculate the internal FIFO size for the target Ethernet application
See how an IP core can easily be configured for different on-chip interfaces and applications
Learn how to include an Ethernet design into a reusable processor independent subsystem using the DesignWare® IP for AMBA® in conjunction with the Ethernet IP
Get introduced to the Synopsys DesignWare Gigabit Ethernet IP solution, including multiple PHY interfaces.
Presenter:
John A. Swanson, Senior Manager, Synopsys
John A. Swanson has been working in the IP business since 1990 when he joined Logic Automation / Modeling which was later acquired by Synopsys. John has worked in the design, verification, integration and implementation aspects of complex IP in engineering, methodology, business development and marketing. He has been working on System-on-a-Chip technologies and methodologies for over ten years with Synopsys in a variety of assignments. Currently he is the product line manager for the DesignWare Ethernet family of Digital cores as well as JPEG, 1394 and the IP Reuse tools. He also is active in many standards activities.
Prior to joining Synopsys he worked for Amoco Oil Company designing wellhead automation and control systems. He is an Honor graduate from DeVry Institute of Technology where he completed his engineering degree with Presidents List honors.
|
