|
|
|
On-Demand Webinar |
|
 |
|
|
|
|
| FPGA Design Efficiency with Synthesis for ispLEVER |
|
Overview:
Learn how to be more efficient and get better results using Synplify synthesis with ispLEVER implementation tools. Understanding tool options, data flow, and source code constraints can make the RTL-to-implementation loop more efficient.
This webcast will cover the following areas:
- Synthesis and implementation data flow
- Understanding synthesis and back-end place and route user constraints
- Evaluating design performance and utilization from output reports
- Tips for design organization
- Managing IP cores
- Scripting to automate design runs
Drawing:
- 1 participant who attends the live broadcast and fills out the feedback form will receive an ispLEVER Development Tool for Lattice programmable logic design. Official Rules
Presented by:
 Troy Scott, Senior Product Marketing Engineer, Lattice Semiconductor
Troy Scott is a marketing specialist at Lattice Semiconductor Corporation. He has more than 15 years experience in the EDA and semiconductor industry. Troy's background includes HDL synthesis and simulation, hardware emulation, and IP evaluation and marketing. Troy holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.
|
|
|
|
| Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance ISP Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Analog Components (PAC), and Programmable Digital Interconnect (GDX). Lattice also offers industry leading SERDES products. For more information, visit www.latticesemi.com. Lattice Semiconductor Privacy Policy. |
|
|
| |
|
|
|
|
|
|
 |
Related Companies |
 |
|
|
|
|
| |
|
|
|
|
