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On-Demand Webinar |
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| Logic Designers: Recapture control to achieve predictable closure on your project goals |
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Overview:
You are invited to attend a webinar outlining a new approach to designing for performance in the context of your overall project goals. A "performance at all costs" approach is no longer feasible given today's chip design challenges. This webinar will outline a new powerful front-end methodology along with state-of-the-art technologies and techniques that deliver more efficiency and predictability in closure on your performance goals while managing the increasing factors of power consumption, cost, and schedule. Some highlights include:
- Physically aware global synthesis - A new and unique approach that combines well-proven global synthesis and silicon virtual prototyping technologies to provide real physical interconnect timing to the logic design process. This solution scales from the RTL block design to the chip-level interconnect level to deliver the appropriate amount of physical feedback to drive global logic optimization and to help logic designers make the decisions that ultimately affect the final performance, power, and size of the chip.
- Formally validated constraints - Check design constraints for correctness, validate false paths functionally, and pinpoint real design issues quickly. The result is a much more efficient process to improve constraints, which will reduce re-spins, eliminate manual errors, and speed closure on timing, power, and area goals through implementation.
- Productive signoff static timing analysis (STA) - Silicon accurate signoff timing analysis coupled with a productive analysis environment speeds the pinpointing of timing issues. This front-to-back timing analysis environment enables faster convergence and design closure with physical implementation.
Please join us in this compelling webinar and hear what all the excitement is about.
Who should attend?
- Engineering managers
- RTL designers
- Front-end synthesis users
- Engineers or technical managers interested in improving engineering productivity, achieving more rapid design closure, improving closure on timing, power, and area goals, and minimizing iterations between front-end and back-end implementation teams.
Presenters:
 Jack Erickson, Product Marketing Director, Cadence Design Systems, Inc.
Jack Erickson is a Product Marketing Director for synthesis and logic design at Cadence Design Systems, Inc. In his 14 years at Cadence he has held numerous technical and marketing roles including synthesis, simulation, equivalence checking, physical synthesis, and floorplanning. He holds a BSEE from Tufts University and an MBA from Worcester Polytechnic Institute.
 Shahzad Chowdry, Member of Technical Staff and Co-Founder of Symmid Semiconductor Technology
Member of Technical Staff, is a co-founder of Symmid Semiconductor Technology (SST), a Silicon Valley based ASIC Design Services firm specializing in low power and high performance RTL to GDSII design work. Shahzad has 15 years of experience in ASIC design and applications engineering with expertise in logic synthesis, power optimization, DFT, and timing closure. Prior to starting SST, Shahzad worked for various firms in the EDA, semiconductor and systems industries.
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| Cadence Design Systems is the world's leading EDA technologies and engineering services company. Cadence helps its customers break through their challenges by providing leading-edge electronic design solutions that speed advanced IC and system designs into volume production. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards, and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence Privacy Policy. |
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