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On-Demand Webinar |
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| Towards True Co-Design: Bridging the Gap between IC and Package Design for Power Integrity |
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Overview:
For many years, the need for chip-package co-design to rapidly meet increasingly tight signal and power integrity (SI/PI) constraints in a cost-effective way has been more than obvious. Increasing functional integration, higher speed input-output signaling, and low-power design techniques have continued to exacerbate this need. "Co-design" as it is practiced today, however, is often little more than isolated design of the chip and package followed by co-optimization across product generations. Existing EDA tools and analysis techniques address SI/PI issues at the package and chip levels, but not with an integrated approach, which is needed for accurate and actionable tradeoff analyses.
In this webinar, we explore the symmetrical use of package-aware chip analysis and chip-aware package analysis to address true IC-Package co-design. The chip-package core power delivery network (PDN) is analyzed for static IR drop and dynamic voltage drop (DvD), pointing to design improvements through floor planning, decoupling capacitance, and wire-bonding design. Including the I/O subsystem as well enables assessment of timing metrics (e.g. jitter) and simultaneous switching output (SSO) noise, pointing to design improvements available through voltage domain partitioning and impedance control. Due to the unique awareness of both the chip and package, tradeoffs in chip versus package complexity emerge as a new design freedom to meet performance and cost demands.
What will be covered:
In this educational webinar, Apache and Optimal will detail the methodology and technology used for integrated IC-Package co-design. The webinar will include several design examples to illustrate system design issues and their resolution. Specifically, the webinar will discuss:
Impact of package on chip power integrity
Methodology for power analysis with consideration of package impact
Technology for generating core power delivery network
Use of chip power model in package design
Who should attend:
Physical designers working on designs especially at 90nm or below
Signal integrity engineers
Package design engineers
Design methodology and design architects
Presenters:
Emre Kulali, Senior Applications Engineer, Apache Design Solutions
Currently, Emre is the lead applications engineer for Apache's newly introduced Sentinel product line, addressing the IC-Package power and signal integrity challenges. Prior to joining Apache in 2004, he held various engineering positions with OEA International Inc. and CoWare Inc. Mr. Kulali holds a Bachelors of Science in Physics & Mathematics from St. Lawrence University, N.Y. and a Masters of Science in Engineering Management from Santa Clara University.
Marc Kowalski, Senior Applications Engineer, Optimal Corporation
Marc is directly engaged with a number of clients advising on the combined use of Apache's RedHawk and Sentinel tools with Optimal's PowerGrid and PakSI-E. Dr. Kowalski has a broad background in the use of computational field solvers in areas including high-speed signaling, remote sensing, and high energy physics. He has published extensively in the peer-reviewed literature in this area and is an elected member of USNC Commission B. He earned the Ph.D. in electrical engineering from the University of Illinois at Urbana-Champaign and has served in various engineering and program management roles under support from the U.S. Departments of Energy, Homeland Security, and Defense at the Stanford Linear Accelerator Center (SLAC) and L-3 Communications.
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| <b>Apache Design Solutions:</b><br><br>
Apache delivers the leading power sign-off solution adopted by 80% of top IDMs, fabless semiconductor companies, and foundries, as well as complete platform solution for silicon integrity of SoC, analog-IP, and system designs. Apache's innovative platform considers all sources of noise that impacts the design--such as power, signal, package / system I/O, substrate, and temperature--Apache's silicon integrity platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon / system. Apache's vendor-neutral solutions enable designers to adopt any industry-standard physical design flow and are in production use by over 40 customers worldwide. For more information, visit <a href=http://www.apache-da.com target=_blank>www.apache-da.com</a>.<br><a href=http://www.apache-da.com target=_blank><font size=1>Privacy Policy</font></a><Br><br>
<b>Optimal Corporation:</b><br><br>
Optimal Corporation is a leader in 3D power, signal and thermal integrity analysis for IC Package, System-in-Package (SiP) and PCB design. Its innovative solutions enable design teams to concurrently analyze and optimize the IC with the package and the packaged IC on the PCB. Through seamless integration with all of the major CAD design flows, its solutions help customers achieve fast and efficient design time. Optimal, founded in 1995, is a TSMC Technology Alliance Partner and a member of the Apache Design Automation Partners Program. Optimal Corporation is headquartered in San Jose, Calif. For more information, visit: <a href=http://www.optimalcorp.com target=_blank>www.optimalcorp.com</a>.<br>
<a href=http://www.optimalcorp.com/company/overview.html target=_blank><font size=1>Privacy Policy</font></a> |
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