|
|
|
On-Demand Webinar |
|
 |
|
|
|
|
| High-Speed Serial Interface Testing - Solving The Analog Test Problem With A Fast And Accurate Digital Solution |
|
| Select 'Register' to attend this event or 'View Series' for more information on Synopsys DesignWare IP Webinar Series 2007 |
|
Overview:
The move to integrated high-speed serial interfaces such as PCI Express, SATA and XAUI has brought new challenges in terms of production testing. The goal is to test these mixed-signal serial links with maximum fault coverage while utilizing the minimum amount of test time. The conventional approach using simple "external loop-back" are fast but not accurate, while expensive, sophisticated mixed-signal testers burden the user with additional overhead costs and having to write and debug complex test programs. To address this challenge, this webinar will show how Synopsys has implemented a built-in test solution for its DesignWare® PCIe®, SATA and XAUI PHY IP, where at-speed analog test can be done on a pure digital tester running at 10 MHz. This enables the user to generate verified pure digital test patterns for the all the important compliance tests and more, including eyemask, asynchronous voltage margining and transmit level testing. These tests can be generated by the user in less than 5 minutes with little no knowledge of the high-speed link - all with a push of a button. Using this capability, customers have gone from 1st silicon to production test in under two weeks.
Products Featured:
DesignWare IP
PCI Express PHY
SATA PHY
XAUI PHY
Who Should Attend:
- ASIC design engineers
- Designers of complex, high-performance systems
- System architects
- Engineering or technical managers
Moderator:
 Clive "Max" Maxfield has now spent over a quarter of a century in the electronic, computing, and EDA arenas. In 1980, after obtaining his BSc in Control Engineering (an interesting mixture of math, electronics, mechanics, and hydraulics and fluids), Max joined a design team at International Computers Limited (ICL) creating CPUs for mainframe computers. In addition to designing ASICs and circuit boards, Max has written numerous test programs for functional and in-circuit testers. In the area of digital logic simulation, Max has created models of everything from ASIC cell libraries to microprocessors. Due to his digital expertise, Max was once appointed analog marketing manager at a large EDA company (the world is a funny old place sometimes).
In the early 1990s, Max thought it would be fun to see a book he'd written on the shelves in his local book store, so he penned his first tome Bebop to the Boolean Boogie (An Unconventional Guide to Electronics). Since that time, Max has authored and co-authored a number of books, including EDA: Where Electronics Begins, The Design Warrior's Guide to FPGAs, and How Computers Do Math (Featuring the Virtual DIY Calculator).
Presenters:
 Dr. Robert Lefferts, PhD, Director, Hillsboro PHY Development (HiPHY)
Dr. Lefferts has more than 25 years of experience in the semiconductor industry. He received his PhD in Electrical Engineering from Stanford University in 1981. He is currently the director of the Hillsboro PHY development group which is responsible for Synopsys' high speed SERDES IP serving PCIe, SATA, and XAUI applications. Prior to Synopsys, he was the Director of Engineering at Accelerant Networks, a fables semiconductor company in the high speed transceiver market that was acquired by Synopsys in 2004. His interests include high speed SERDES and analog design, technology development, design support, and semiconductor device modeling and characterization. Prior to Accelerant Networks, he worked at Lattice Semiconductor, where he was responsible for all aspects of design integrity and cell reliability for advanced CMOS nonvolatile programmable logic devices.
 Joe Giuliano is the Manager of the Serdes Application, Test and Product engineering group at Synopsys. He has 20+ years experience in the semiconductor industry. Over his career he has worked at National Semiconductor, Lattice Semiconductor and Accelerant Networks. He graduated from California Polytechnic University San Luis Obispo with a degree in Electrical Engineering.
|
|
|
|
| Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading system and semiconductor design and verification platforms, IC manufacturing and yield optimization solutions, semiconductor intellectual property and design services to the global electronics market. These solutions enable the development and production of complex integrated circuits and electronic systems. Through its comprehensive solutions, Synopsys addresses the key challenges designers and manufacturers face today, including power management, accelerated time to yield and system-to-silicon verification. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com |
|
|
| |
|
|
Original Broadcast Date |
|
|
Jul 12, 2007
|
| |
|
|
|
|
| Synopsys DesignWare IP Webinar Series 2007 |
|
|
| |
|
|
|
|
|
 |
Related Companies |
 |
|
|
|
|
|
|
|
| |
|
|
|
|
