Overview:
Analog IC designers face increasing challenges in the design and verification of analog blocks and intellectual property. The fact that standards are getting ever more stringent is imposing tighter specifications on analog blocks. These blocks are now larger, include more functionality, operate at higher frequency and are more susceptible to noise and crosstalk from neighboring digital blocks. Even more challenges emerge as analog designs migrate to advanced process nodes. Some examples include gate leakage mismatch exceeding conventional matching tolerances, nonlinear output conductances along with reduced gain and limits on linearity, and wide process variations requiring detailed statistical analysis. Additionally, parasitics are of paramount importance and have a first order impact on circuit performance. Interconnect parasitics and coupling among devices, interconnects, and passives need to be accurately taken into account during design. Otherwise, it could take months for an analog design to achieve layout and parasitic closure.
This webinar will show how Cadence Virtuoso Multi-Mode Simulation together with Cadence QRC Extraction provide a complete analog design verification solution that includes accurate device and interconnect parasitic extraction and fast Monte Carlo analysis to ensure reliable designs that meet performance, power, and noise specifications.
Products featured:
- Virtuoso Multi-Mode Simulation
- Virtuoso Spectre® Circuit Simulator L
- Cadence QRC Extraction
- Virtuoso Analog Design Environment
Who should attend:
- Analog designers and team leads building analog blocks and intellectual properties from amplifiers, filters and bandgap references to analog to digital converters, phase locked loops and clocks and data recovery circuits
- Designers porting analog circuits to advanced process nodes
- CAD engineers supporting 65/45nm flows
- Verification engineers
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