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On-Demand Webinar |
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| Power Analysis Using RedHawk from Early Design to Signoff |
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Overview:
As designs are manufactured at 90nm process nodes and below, power integrity has become one of the critical signoff requirements. The designers are faced with the challenges of managing power from early in the design process, as well as ensuring a highly reliable power grid design prior to tape-out. And they are required to accomplish all of this while improving productivity.
Join Apache Design Solutions to learn how RedHawk, the industry's defacto standard in SoC power sign-off, can provide designers with the ability to estimate, analyze, optimize, and validate their power grid design - from floor planning through silicon signoff. RedHawk is a complete SoC power and noise solution, with single layout extracted database, high-speed / high-capacity full-chip transient simulation engine, and a unified debugging and analysis environment. It has been adopted as a signoff solution by 80% of the top IDM, fabless semiconductor, and foundries, and is certified by TSMC's reference flow 7.0.
What will be covered:
In this educational webinar, Apache will detail their comprehensive silicon integrity solutions for SoC power - spanning from early design to signoff. Specifically, the webinar will discuss:
- RedHawk capabilities and its application throughout different stages of the design flow
- Methodology for early design analysis, including grid prototyping and decap optimization
- Post layout power grid analysis and optimization, including impact on timing and design margin management
- Examples of design analysis results and performance metrics
Presenter:
Aveek Sarkar, Vice President of Product Engineering and Support
Mr. Sarkar is currently the Vice President of Product Engineering and Support for Apache Design Solutions, where he is responsible for overseeing worldwide customer support and product engineering for all of Apache's products. Prior to joining Apache, Mr. Sarkar worked for several years in Sun Microsystems on several generations of UltraSparc processors. He also held engineering positions at Cadence and National Semiconductor Corp. He holds a B.Tech from the Indian Institute of Technology, Kanpur, a MS EE from Oregon State University, and a MBA from Santa Clara University.
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Apache delivers the leading power sign-off solution adopted by 80% of the top semiconductor companies and a complete platform solution for silicon integrity of low-power, high-performance system-on-a-chip (SoC) designs. Apache's innovative platform considers all sources of noise that impacts the design--such as power, signal, package / system IO, substrate, and temperature--enabling designers to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache's vendor-neutral solution supports any industry-standard physical design flow and is certified by TSMC's 5.0, 6.0, and 7.0 Reference Flow. Apache is a global company with R&D centers and direct sales / support offices worldwide. For more information, visit www.apache-da.com
Apache Design Solutions, NSPICE, RedHawk, PsiWinder, Sahara-PTE, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc. |
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