CMP - United Business Media TechOnline
All Articles Products Courses Papers VirtuaLabs Webinars Web
 
LoginRegister
      TechOnline > Learning >  Technical Paper
Technical Papers
Boosting RTL Verification with High-Level Synthesis

Click to Download
pdf logo
Mentor Graphics Technical Library
December 15, 2009
 

Mentor Graphics

Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creating bug-free RTL designs. This can be realized today by automating the generation of RTL from exhaustively verified C++ models. If done correctly, high-level synthesis (HLS) can produce RTL that matches the high-level source specification and is free of the errors introduced by manual coding.

Note: By clicking on the above link, this paper will be emailed to your TechOnline log-in address by Mentor Graphics.

 
Rate this paper
WORSE | BETTER
1 2 3 4 5

submit a paper
Follow Tech Papers

Mentor Graphics
   

COURSE
1. Getting Started with Android Development for Embedded Devices

TECH PAPER
2. New Tools Answer Old Issues in Wiring Harness Design

TECH PAPER
3. Developing a Complete Critical Feature Analysis Solution—Part 2: Defining CFA Metrics

TECH PAPER
4. Developing a Complete Critical Feature Analysis Solution—Part 3: Parameter Weightings for CFA Metrics