Jocelyn Moreau and Jayant D'Souza
STMicroelectronics and Mentor Graphics

STMicroelectronics' advanced designs have to meet rigid targets for manufacturing test coverage, which includes identification of new failure mechanisms. Achieving the highest quality testing for these devices requires adding deterministic patterns that include coverage for at-speed and bridging defects. Because of this greater data volume, we use scan compression during production test. Devices such as image sensors and smart cards have very small pin interfaces, and a majority of the pins are analog which cannot be shared for digital test. This is especially challenging when only three digital pins are available for interfacing to the automated test equipment (ATE).

To address this challenge, we used a new interface to the tester that enabled us to run compressed automatic test pattern generation (ATPG) patterns with only three pads. This article describes how the interface can be used to achieve higher test quality in such devices.