Zibi Zalewski
Aldec

Verifying FPGA, PLD and ASIC designs in hardware, while tracing the output results back to the original design requirements, is a significant challenge with today's DO-254 verification solutions. This article provides information concerning using the more traditional approach to solving these difficulties versus the use of "In-Hardware" simulation. The information herin concerns the Aldec DO-254 Compliance Tool Set (DO-254CTS).