Ron Press
Mentor Graphics

The manufacturing test process for integrated circuits (ICs) is increasing in cost and effort in order to keep up with rigorous quality standards, the complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins. Reduced pin count testing (RPCT) is a technique used to reduce the cost of testing by minimizing the pin requirements of a device when tested on an ATE.

By combining RPCT with test compression, we have extended the capabilities of multi-site testing to allow application of at-speed test patterns using low-cost testers that are seriously pin-limited. The method proposed in this paper enables gains in test coverage with less application time and minimal effects on design and test overhead. It can be used in multi-site test, with simpler fixturing.