Nusym

Verification of electronic products has evolved considerably over the last twenty years. Achieving the confidence that a design is functionally correct has become more difficult due to increased design size, complexity and time-to-market pressure. To counter these problems, faster simulators and specialized verification languages have been introduced. Based on these advances, constraint-based random testing with a focus on attaining exhaustive functional and structural coverage has emerged as the state-of-the-art method for achieving verification closure. However, this is fundamentally a black box technique that will not be able to keep up with increasingly complex designs. The next big advance in verification will come from tools that provide insight into the design while using existing infrastructure and methodologies.

This paper introduces a verification technology called "path tracing," which leverages existing testbenches to extract insight into both what the design does and what it should do. This is used to intelligently and automatically drive the verification process to achieve coverage closure, significantly increasing both design confidence and verification efficiency.