Bob Naber and Nitin Deo
Cadence

As semiconductor companies move to more advanced technology nodes, integrated circuit (IC) design teams find more manufacturing effects exerting a larger impact on silicon performance and yield. Designers using traditional methods continue to face significant challenges in reliably meeting yield and performance objectives for current technologies—and will encounter more serious limitations at next-generation technology nodes. This paper discusses new approaches based on flexible, accurate modeling methods. These approaches allow engineers to exploit manufacturing knowledge early in the design flow in order to avoid yield problems.