Mike Fingeroff and Thiagaraja Gopalsamy
Mentor Graphics and Altera

Today's class of high-performance FPGAs, such as the Altera Stratix III, provides design engineers with a hardware platform capable of meeting the computational requirements of many next-generation wireless and video algorithms. However, although these devices provide dedicated hardware for implementing the basic building blocks of digital signal processing (DSP) algorithms, designers must still take an algorithm from concept to implementation in Register Transfer Level (RTL).

The conventional, manual design method of modeling the algorithm functionality in a high-level language such as C++ and then hand-coding it in RTL is not only time-consuming and error prone, but also highly sensitive to back-end routing delay problems. This paper introduces an alternative method: combining Catapult's ASIC capabilities with Altera Accelerated Libraries. This approach provides designers with a rapid path from algorithms modeled in ANSI C++ to optimized RTL running in FPGA hardware.