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Video Coding Using Digital Signal Processors

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1999 International Conference on Signal Processing Applications and Technology (ICSPAT) Paper
235 KB (13 pages)
November 4, 1999
 

Iain E.G. Richardson, Kathy Kipperman, Gillian Smith, and Martyn Riley
4i2i Communications

Video coding algorithms such as H.261, H.263 and MPEG have traditionally been implemented using dedicated ICs. The demanding signal processing required for video compression has made it difficult to achieve high frame rates with software implementations. However, the processing power of the latest DSP platforms makes realtime video coding possible. In this paper we present a case study of a DSP implementation of the H.263 standard. We show how software restructuring and optimization, together with careful choice of processing algorithms, enables real-time video coding on a DSP platform.

A video encoder compresses a series of video frames to produce a low bit-rate data stream that can be efficiently transmitted or stored. A video decoder reverses this process to recreate the video frames (the quality of the reconstructed frames is generally not as good as the original).

A number of International Standards describe video coding systems for different applications. These include JPEG for still image compression, MPEG-1 for "entertainment" digital video, MPEG-2 for digital television and H.261/H.263 for video conferencing and video telephony. In this paper we concentrate on the H.263 standard: however, many of the techniques described here are applicable to the other main video coding standards.

 
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4i2i Communications
ICSPAT
   

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1. An Overview of Video Compression Algorithms

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2. Processor Architecture for High Performance Video Decode

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3. The Relationship of Dynamic Range to Data Word Size in Digital Audio Processing

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