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Achieve Faster Timing Closure with Graph-Based Physical Synthesis

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Xcell Journal Article
267 KB (2 pages)
December 1, 2005
 

Jeff Garrison
Synplicity

Advances in FPGA technology have opened the door wide open for use in all types of applications, including wireless communications, computer, industrial, defense/aerospace, medical, automotive, and even consumer. Xilinx® Virtex™-4 devices have the capacity, performance, and cost structure to lead a migration from traditional cell-based ASICs to programmable devices in all but the highest volume and bleeding-edge applications. Along with this capability, however, are new challenges from a designer's perspective. In this article, I'll discuss a solution to one of these most important challenges—timing closure.

Reprinted with permission from Xcell Journal / Fourth Quarter 2005. Article © Xcell Journal.

 
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