Olivier Despaux
Xilinx

This application note describes a 200-MHz DDR SDRAM (JEDEC DDR400, PC3200 standard) controller implemented in a Virtex-4 XC4VLX25 FF668-10CES device. This implementation uses direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines.

DDR SDRAM devices are low-cost, high-density storage resources that are widely available from many memory vendors. This reference design has been developed using DDR400 SDRAM components and DIMMs.