Karen Chow
Mentor Graphics

While nanometer technology enables more and more functionality on a single chip, it also brings a host of new physical effects that must be accounted for in simulation and modeling. Finer line widths, longer interconnect, more routing layers and burgeoning analog content are just the top of the iceberg; lurking below are via capacitance, poly-contact coupling, planarity fill, antenna effects, copper processing issues, parasitic inductance and much more that can produce functional flaws, which many times result in failed silicon and costly respins. By implementing an advanced nanometer silicon modeling flow, designers can account for the complex device and interconnect issues that so profoundly affect the accuracy of analysis and successful manufacture of a design.