John Ferguson
Mentor Graphics

System-on-chip (SoC) design combines individual components created by various design groups, and developed using numerous design styles, methodologies and knowledge levels. Despite the functionality strength realized by this engineering diversity, each component must meet a common standard during development-the physical verification requirements of the foundry or manufacturer. As designs become larger and more complex, and design rules become more numerous, greater demand is placed on EDA toolmakers to develop tools and methodologies that not only help streamline the design process through efficiency and accuracy, but also accommodate various design styles while establishing a common standard across the industry. Adopting a single physical verification and extraction flow will not only streamline the SoC design process, thereby saving time and resources, but also act as the glue that binds the many components into a cohesive system. Choosing EDA tools that not only meet the rigorous internal verification standards set by the foundry, but also are widely adopted throughout the industry, ensures confident design and data transfer among SoC providers.