Ian Smith, Marko Suominen, and Marius Sida
Mentor Graphics

Today's mixed-signal RF IC designs present many challenges and require an integrated, easy-to-use design and verification flow. One of the primary challenges is post-layout verification, where many physical effects impact the quality and performance of the complete design. In situations where rapid pre- to post-layout turnaround is key to meeting project deadlines, new scenarios must be investigated to increase productivity, and trade-offs must be made during the design and verification process. In this article, we will introduce new inductor device generators, which offer dramatic efficiency increases in the development and automation of RF IC design, layout creation and verification. The flexibility and ease-of-use of these device generators, which fit into the Mentor Graphics AMS SoC Design Flow, make them very attractive to any RF IC Designer.