Nandu Tendolkar, Rick Wollenberg, and Rajesh Raina, Motorola Xijian Lin, Bruce Swanson, and Greg Aldrich
Motorola and Mentor Graphics
Scan-based at-speed testing presents new challenges for the fastest chips. This white paper describes the renewed interest in at-speed testing from VLSI designers and the associated challenges faced by the design teams in equipping their designs with appropriate DFT to enable at-speed testing.
Note: By clicking on the above link, this paper will be emailed to your TechOnLine log-in address by Mentor Graphics.
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