Brian Doyle, Reza Arghavani, Doug Barlage, Suman Datta, Mark Doczy, Jack Kavalieros, Anand Murthy, and Robert Chau
Intel
We have fabricated conventional planar transistors of various gate lengths down to as small as 10nm polysilicon gate lengths, in order to examine transistor scaling. At 30nm gate lengths, the devices show excellent device characteristics, indicating that this node can be met with conventional transistor design. At lower gate lengths of 20 and 15nm, the devices still maintain excellent device characteristics and follow traditional scaling with respect to gate delay and energy delay, although off-state leakage and gate leakage do increase. At 10nm gate lengths, the transistors continue to function as MOS devices, but they are limited by off-state leakage.
One feasible method of significantly improving off-state leakage is through reducing the sub-threshold gradient. We show that Depleted Substrate Transistors (DST), a broad category of devices that include single- and double-gate transistors, whose active channel region stays fully depleted during operation, can achieve near-ideal sub-threshold gradients and a reduction in off-state leakage of at least two orders of magnitude over bulk transistors. We believe that DST architecture will adequately address transistor scaling needs down to 10nm gate lengths.
In addition to DST device architecture, new electronic materials and modules will be needed to maintain high performance and low-parasitic leakages. As an example, to alleviate increasing gate leakage, changes in the gate stack are necessary. Replacement of SiO2, the workhorse of the industry for over 30 years, with a high-K dielectric will be required. Other changes will include use of raised source/drain, metal gate electrodes and channel engineering.
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