Lavi Lev, Rahul Razdan, and Christopher Tice Design Systems
Cadence Design Systems

Functional verification of nanometer-scale ICs is all about effective use of time, terms of speed and efficiency. Yet today's fragmented functional verification processes make it impossible to optimize either. Every design task has its own separate verification stage, resulting in numerous unique verification stages. Each stage has its own methodology, environment, tools, languages, models, user interfaces, APIs and, often, even its own specialized verification engineers. Engineers create almost everything from scratch at every stage, leaving the preceding stage to rot. The result is an expensive, slow, inefficient process that all too often allows critical bugs to reach silicon. Techniques such as automatic test generation and assertions during RTL simulation, sometimes known as "smart verification," apply to only a single verification stage and thus cannot even begin to address fragmentation.

This paper describes the requirements for high-speed, high-efficiency functional verification of nanometer-scale ICs. The paper first examines the primary verification drivers—massive digital logic, massive embedded software, and critical on-chip analog circuitry. It then describes a unified verification methodology—one that supports verification from system design to system design-in—across all design domains.