Cadence Design Systems

This paper describes a design methodology for the implementation of multimillion-gate, nanometer system-on-a-chip (SoC) designs. This new methodology is based on the creation of a physical prototype early in the back-end design process. This prototype generates in a fraction of the time required to complete the traditional back-end flow, but still maintains very high correlation with the final design.

In nanometer design, wiring delay accounts for the vast majority of overall delay. Unless you get to the wires, the estimates of delay can be up to 10 times off. Physical prototyping allows you to get to the wires fast. In addition, it provides the benefit of optimal partitioning for hierarchical designs.