Lavi Lev and Ping Chao
Cadence Design Systems

Implementing nanometer-scale ICs begins and ends with wires. Wires are so dominant that little is known about a design's performance or manufacturability without them. In fact, nanometer design strategies that are not clearly focused on rapid wire creation, optimization, and analysis are destined to fail.

This paper describes the requirements for an effective, reliable IC implementation platform for the 90 nm process node and beyond. It begins with a description of the central role wires play in nanometer design and why traditional linear design flows are insufficient. It then describes a new continuous convergence methodology, which has proven highly valuable at 0.13 micron and will be absolutely necessary at 90 nm.

Next, the paper describes the key implementation, analysis, and database technologies needed to enable this methodology. Implementing nanometer designs requires nanometer routers that optimize wire creation for both performance and manufacturability. Verifying nanometer designs requires nanometer analysis tools that accurately model physical effects as they would occur in the target silicon. Efficiently representing these designs—most of which will be large digital designs with critical analog circuitry—requires unified nanometer databases with massive capacity and efficient extensibility.

Wires must be the centerpiece of any nanometer methodology. Without such a methodology, design teams will not be able to create massively complex nanometer ICs in a timeframe of relevance.