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Live Webinar |
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| Using the New SystemC TLM-2.0 Standard for the Creation of Virtual Platforms for Software Development and Architecture Design |
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Overview:
The new SystemC TLM-2.0 standard from the Open SystemC Initiative (OSCI) is aligning the industry, enabling the creation of truly interoperable SystemC-based virtual platform models. This 1 hour CoWare webinar gives a technical overview of the key elements in TLM-2.0 and illustrates the effective creation of standards-compliant TLM-2.0 models that satisfy the simulation speed and timing accuracy requirements of different ESL design tasks including software development, hardware and software performance analysis, and architecture design.
What you will learn:
The audience will first learn about the key elements in the TLM-2.0 standard:
- The Loosely Timed (LT) modeling style
- The blocking transport API
- The generic payload data structure
- Temporal decoupling and synchronization
- The Direct Memory Interface
- The Approximately Timed (AT) modeling style
- The non-blocking transport API
- Approximating bus protocols with the AT API
- Convenience sockets for seamless integration of LT and AT models
- Extension mechanisms
After this overview we will show the effective creation of TLM-2.0 compliant models by using modeling libraries to hide complexity, save time, and ease modeling effort, including:
- The CoWare SystemC Modeling Library (SCML) for the creation of highly efficient and re-usable TLM-2.0 based peripheral models
- Mixing TLM-2.0 models with legacy models on different levels of abstraction
The webinar concludes by illustrating the practical usage of TLM-2.0 in the context of a CoWare virtual platform for two specific design tasks:
- A Loosely Timed virtual platform for software development and software performance analysis
- An Approximately Timed virtual platform subsystem for SoC architecture design
Presenter:
 Tim Kogel received his diploma and PhD degree in electrical engineering with honors from Aachen University of Technology (RWTH), Aachen, Germany, in 1999 and 2005 respectively. He has authored a book and numerous technical and scientific publications on electronic system-level design of multi-processor system-on-chip platforms.Today, he is working as a Principal Solution Specialist at CoWare Inc. In this position, he is responsible for the product definition and future direction of CoWare's SystemC-based Platform Architect product line. His special interest is in SystemC modeling methodology and he represents CoWare in the SystemC Transaction Level Modeling related standardization committees from OSCI and OCP-IP.
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| CoWare is the leading global supplier of platform-driven electronic system-level (ESL) design software and services. IP, semiconductor, and electronics companies use CoWare ESL 2.0 solutions to design better processor- and software-intensive products — faster. CoWare solutions solve the new design challenges associated with platform architecture design, platform verification, application sub-system design, processor design, DSP algorithm design, and software development, and are based on open industry standards including SystemC. These solutions also enable IP and semiconductor companies to implement more effective go-to-market strategies. CoWare's corporate investors include ARM [(LSE: ARM); (NASDAQ: ARMHY)], Cadence Design Systems (NASDAQ: CDNS), STMicroelectronics (NYSE: STM), and Sony Corporation (NYSE: SNE). CoWare is headquartered in San Jose, Calif., and has offices around the world. For more information about CoWare and its products and services visit http://www.coware.com. CoWare Privacy Policy |
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Date and Time |
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| Greenwich Mean Time |
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Tue., May 20, 2008 16:00
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| Eastern Daylight Time |
| Tue., May 20, 2008 12:00 PM |
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| Pacific Daylight Time |
| Tue., May 20, 2008 09:00 AM |
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System Requirements
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