DESCRIPTION

Get on the road to faster debug, reduced variability and simpler, smaller checks and decks. This free web seminar will explain how your foundry, peers, and potential competitors have prepared themselves for the challenges of advanced verification - driving down cycle time in order to get to market faster.

Advanced physical verification requires a new approach:

• Classic 1D physical verification approaches cannot ensure that designs will meet design variability and performance.


• Continued use of classic physical verification approaches exacerbates the explosion of deck size, run time and debug time.


• Products Covered: IC Design and Circuit Design Verification, IC Verification & Signoff Using Calibre, Physical Verification, Calibre nmDRC, Calibre RVE, Circuit Verification with Calibre, Calibre nmLVS

INTENDED AUDIENCE
Design Verification Engineers and Managers, CAD Engineers and Managers, Design Rule Definers and Writers, Anyone working in the physical verification area of design

ESTIMATED TIME
60 min.

AUTHOR