DESCRIPTION
ARM's success to date has been largely due to its remarkable performance/power (MIPS/Watt) rating, and this will likely continue to be its most critical benchmark for future applications. This class considers how attention to interdependent detail in cache controller design, conditionally executable instructions, intelligent voltage management, and interrupt control hardware contribute to the ARM architecture's high performance and low power operation.

PREREQUISITES
Course Price $19.95
Basic Computer Architecure knowledge.

ESTIMATED TIME
85 minutes

AUTHOR