ESC SV-432- Understanding Multi-Core Embedded O/S Issues

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ESC SV-432- Understanding Multi-Core Embedded O/S Issues
Michael Anderson Chief Scientist, The PTR Group, Inc.

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DESCRIPTION Multi-core CPUs are not just for "big iron" applications. Many traditional embedded CPU architectures are now supporting multiple CPU cores as well. This class outlines the issues with processor affinity, interrupt/process/thread scheduling, mutual exclusion, and cache coherency concerns when executing on a multi-core CPU. This class examines the low-level operating system features that support multi-core operation. In addition, this class helps set expectations for performance enhancements when running on these newer architectures. PREREQUISITES Course Price $19.95 Thorough background in "C" and be familiar with embedded operating system concepts. ESTIMATED TIME 95 minutes AUTHOR

Michael Anderson Chief Scientist, The PTR Group, Inc.

Mike Anderson is chief scientist for The PTR Group, Inc. His background encompasses over 30 years of computer experience ranging from supercomputers to embedded 8-bit microprocessors. He is a former chairman of the VxWorks User's Group and has authored several courses and magazine articles designed to teach real-time and embedded systems programming. Mr. Anderson holds a BA in mathematics from the University of South Florida and an MSCS from George Mason University.

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