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ESC SV-242-262- Introduction to CPLD and FPGA Design, Part 1 and 2
Ben Harding Senior Systems Engineer, SAIC and R.C. Cofer Field Applications Engineer, Avnet
Module
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DESCRIPTION
This class examines the underlying architectures, resources, tools, and design flow steps for CPLD and FPGA programmable devices. An example design is used to teach the design methods for capturing, implementing, simulating, and debugging. A summarized list of best practice design techniques for CPLD and FPGA devices is provided.

PREREQUISITES
Course Price $19.95
Knowledge of digital logic design.

ESTIMATED TIME
191 minutes

AUTHOR

Ben Harding Senior Systems Engineer, SAIC and R.C. Cofer Field Applications Engineer, Avnet
Benjamin Harding is a Senior Systems Engineer for SAIC. He is currently leading the research and development efforts for the Aviation and Missile Research, Development and Engineering Center (AMRDEC) advanced programmable logic lab. Benjamin has extensive embedded design experience in hardware and software across multiple technologies including FPGA, DSP, parallel processing and OS/RTOS. He has implemented embedded system designs with many design techniques and tools including Model-Based design with Matlab/Simulink. He has a BSEE from University of Alabama Huntsville (UAH) and is currently working towards a PHD in Electrical Engineering at UAH. Benjamin is a co-author of Rapid System Prototyping with FPGAs, Elsevier 2005 and has written multiple FPGA design articles.

RC Cofer is a field application engineer for Avnet with 17 years of embedded design experience including real-time DSP algorithm development, board design, debug and integration, transition to volume production, systems engineering, and embedded design project management. His technical focus is rapid system design and prototyping. Utilizing FPGAs in designs allows maximum flexibility while also reducing risk and schedule. He holds a BSEE from Florida Tech, a MSEE in communications and DSP from the University of Florida.
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Embedded Systems Conference (ESC)