ESC SV-161- Power Instruction Set Architecture Quick Start

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ESC SV-161- Power Instruction Set Architecture Quick Start
Paul Gramann Advisory Engineer, IBM

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DESCRIPTION The Power Instruction Set Architecture (formerly PowerPC architecture) is a 32 and 64-bit processor architecture widely used in embedded system designs today. This class presents an overview of the Power Instruction Set Architecture for engineers and programmers who are new to the architecture. The class discusses its storage model, registers, instructions, memory management, interrupt handling, debug facilities and provides suggestions for maintaining code compatibility across different Power Architecture implementations. While mentioning many of the features available in the Power Instruction Set Architecture, this class emphasizes the features available in most of the currently available Power Architecture based embedded processors. PREREQUISITES Course Price $19.95 Some assembler and C programming experience. Due to fast paced, content heavy class, familiarity with microprocessors and processor architecture is desired. ESTIMATED TIME 90 minutes AUTHOR

Paul Gramann Advisory Engineer, IBM

Paul Gramann has over 23 years of experience in embedded systems development and support. In his 13 years with the IBM PowerPC Embedded Processors organization, he has assisted hundreds of customers with PowerPC software and hardware related issues. He currently works with SystemC and ESL models of processor and peripheral components, enabling SOC performance estimation and pre-silicon software development platforms. Paul also authors and reviews technical documentation and develops and delivers technical training for IBM's application engineers and customers. Paul has a BSEE from the University of Virginia and a MSCS from the University of Minnesota.

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