DESCRIPTION
This course provides an overview of the main components within the peripheral subsystem of the MSC711x family, including, but not limited to, the Ethernet MAC, the host data interface (I/F), the Time Division Multiplex (TDM) I/F, the Double Data Rate (DDR) controller, the Phase-locked Loop (PLL)/clock, and the event port. The course presents the characteristics of the Ethernet MAC, host data interface, and TDM module. It introduces the components and configurations of the DDR controller and the features of the PLL/clock and event port. The course answers the question "What is an event?" and provides some examples.

PREREQUISITES
None