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DESCRIPTION
System Verification requires planning the combination of features to
be verified, and the verification techniques to do so. A comprehensive methodology considers the means by which a complete system can be verified, while maximizing the synergy and reuse between each form of verification. Verisity's System Verification Methodology (sVM) is presented, showing how to achieve the most verification using industry best practices, and benefiting from reuse between steps, and between projects.
PREREQUISITES
None
INTENDED AUDIENCE
Verification managers and team leaders responsible for planning, architecting, implementing, and successfully completing comprehensive SoC and HW/SW co-verification projects.
ESTIMATED TIME
45 min.
AUTHOR
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