Designers are looking for new methods to reduce verification time for both simulation models and hardware prototypes. In many ways both of these environments suffer from the same problems of test vector creation, test coverage, analysis of results, and detection of elusive errors caused by temperature and voltage variations. There are many EDA tools and hardware test systems available to help solve these problems in each environment, but in the past there has not been a way to leverage the work done in one environment into the other. Our proposed solution uses a technique called virtual prototyping, which combines traditional test methods with an EDA tool that can translate data back and forth between the Hardware Prototyping Environment and the Design Simulation Environment. This technique effectively unites the worlds of simulation and hardware verification and can take advantage of strengths offered by each environment.