This lecture addresses a family of turbo codes called block turbo code which is based on iterative decoding of product codes. After introducing the concept of product code and soft iterative decoding, simulation results are presented and the iterative decoding process is illustrated through an example. The flexibility of block turbo codes is considered which is very important for practical applications. The second part of the lecture is dedicated to implementation on FPGA or ASIC. Simplifications of initial algorithm and trade off between complexity and performance are considered. Several architectures are considered and their performances are compared with the theoretical one.