This lecture describes step by step, the whole procedure, from the early design stages to the final implementation of a DSP-FPGA based system. The proposed multiprocessing cell will be able to cope with any kind of digital signals, as well as images. Since it is a low-cost hardware easily repeatable in a 2D architecture organization, the developed cell has been conceived with the idea of being used in pipeline procedures. This lecture will present some basic examples of FPGAs programming using VHDL as well as some further examples of DSPs programming using C language.