|
DESCRIPTION
This lecture describes a
methodology to implement FPGA-based FIR filters. The authors use a
VHDL description to design a parameterized, full-parallel, FIR
filter macro-model and have validated the design by compiling
several versions in Altera 10K50-3 FPGAs. The use of DA for FIR
filter design is reviewed and the basic cells used to build the
macro-model is described. In addition, the results of the FPGA
implementation of the FIR filter are shown.
PREREQUISITES
NA
INTENDED AUDIENCE
DSP-based SoC Designers, particulary for
telecom and filtering applications
ESTIMATED TIME
20 min.
|
|
View the complete TechOnLine University Course Guide.
|
|
|
|
| 
