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	Event		Date/Time		Length
	Best of Breed PCI Express IP and VIP Solution for SOC Designers Cadence Design Systems		Feb 12, 2008		60 min.
	Logic Designers: Recapture control to achieve predictable closure on your project goals Cadence Design Systems		Dec 06, 2007		60 min.
	Manage Power at Each Design Stage with a Production-Proven, Holistic Solution to Low-Power Design Cadence		Nov 06, 2007		60 min.
	Circuit-Simulation-Driven RF/Analog System-In-Package Design Cadence		Sep 06, 2007		60 min.
	Accurate Verification of Next-Generation Custom Digital SoC and Memories in 65/45nm Technologies Cadence		Jun 28, 2007		60 min.
	Verification of Next-Generation Mixed-Signal Communication SoC In 65/45nm Technologies Cadence		Jun 21, 2007		60 min.


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