Overview:
With FPGAs so commonly used in high-speed designs, signal integrity issues can be minimized by properly modeling the signal path. This presentation will model real world circuit boards using S-parameters, showing that it is possible to predict eye opening performance before a system is physically prototyped. Both extracted and measured models for interconnects will be used. A 90nm transceiver model is incorporated in Agilent ADS as a new library element, permitting system level modeling of interconnects and FPGA transceivers. Both measured and modeled results are shown and the correlation is discussed, concluding that the new method is both execution time efficient and is sufficiently accurate to provide a high level of confidence for designers wishing to design serial links to 6.375 Gb/s.
Duration: One hour
Who should Attend:
R&D designers, engineers, and project managers working on high-speed digital designs; who spend a significant amount of time in the debug and validation phase dealing with signal integrity related problems in their designs.
 Giveaway:
Registrants who complete the feedback form by September 26th will be entered in a drawing to win one of two autographed copies of Eric Bogatin's book, "Signal Integrity Simplified".Official Rules
Presenters:
Sanjeev Gupta, Signal Integrity Applications Expert, EEsof EDA Division , Agilent Technologies
He has over eighteen years of experience in high frequency design and simulation. Before joining Hewlett Packard, he worked as a high frequency design engineer/scientist at the Defense Research and Development Organization in India. His background includes the design and development of 100 MHz to 100 GHz active and passive circuits for a wide variety of applications. His most recent activity is focused on influencing the Signal Integrity Design Flow in ADS. He received a Master's Degree in Microwave Engineering from the University of Delhi, India in 1988. Sanjeev was awarded the Hewlett Packard President's Award in 1998 for his contributions to the company.
Salman Jiva, Technical Marketing Engineer, Altera
As a senior technical marketing engineer for Altera's high-end FPGA product lines, Salman Jiva is responsible for the technical marketing and analysis of the signal integrity and high-speed interfaces for Altera® FPGAs. Prior to joining Altera, he spent six years at Cisco Systems as an ASIC signal integrity engineer for their enterprise line of switches. Mr. Jiva holds an MS in Electrical Engineering from Santa Clara University with a concentration in communication systems.
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