Overview:
This webinar describes the best-of-breed PCI Express® solution collaboratively developed by Rambus and Cadence. It is engineered to provide the optimal integration and verification experience for Rambus and Cadence customers. This collaboration results in several significant advantages to customers: reduced IP integration effort and time, increased product quality and predictability, and shortened time to market.
The joint solution now delivers proven, high-yielding PHY IPs and highly configurable, feature rich PCI Express digital cores seamlessly integrated and verified using Cadence's mature and uniquely capable verification IP. Cadence verification IP includes the unique Compliance Management System(CMS) tuned for the Rambus IP. CMS has been demonstrated to deliver in excess of 70+% functional coverage without any test writing by customers.
Presenters:
 Pete Heller, Senior Product Line Manager, Cadence Design Systems
Pete is Cadence Design Systems Senior Product Line Manager for Verification IP. Since Cadence acquired Verisity he has been leading Cadence's charge to deliver the world's most capable and differentiated VIP.
 Greg Tanaka, Senior Manager of Sales, Rambus
Greg Tanaka is Rambus' Senior Manager of Sales and Partnerships for PHY
and Digital Design IP. He has spearheaded strategic alliances to give
customers the most complete and best-in-class IP solution available.
 Dheeraj Sharma, Application Engineer, GDA
Dheeraj Sharma is GDA's IP Application Engineer and has been doing high
speed interconnect design and validation with special focus on IP
interoperability and compliance testing. He has been heavily involved
in the validation of Rambus' highly configurable, high-speed
interconnect IP's such as PCI Express, SPI-4.2, and RapidIO.
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