Overview:
In this web seminar, you will learn how Rambus' leadership XDR™ memory architecture addresses the needs of DTV semiconductor and systems designers with superior performance, efficiency, and scalability while lowering overall BOM and enabling faster time-to-market. Supported by three of the top five DRAM vendors, this superior differential technology with patented innovations such as FlexPhase™ and Dynamic Point-to-Point topology, allows unprecedented speeds up to 8GHz using a single DRAM device.
Who Should Attend:
Anyone who specifies or designs any component of a memory subsystem, including:
- Memory Interface PHY Designers
- Chip Architects
- System Designers
- Technical Managers
- Product Marketing
Presenter:
Anil Reddy
Senior Product Marketing Manager
Anil Reddy is the senior product marketing manager at Rambus where he is responsible for product management of the Company's leadership memory and high-speed architecture products. Anil has twelve years of marketing and product management experience in the semiconductor and intellectual property industry, having most recently served as director of worldwide marketing and business development at Conexant Systems. During his tenure at Conexant, Mr. Reddy was responsible for the management of over 80 IP cores, ASSP devices, and Custom ASIC/FGPA design services for the Paxonet™ . Prior to Conexant, Mr. Reddy served as senior product and strategic marketing manager at PMC-Sierra for the network processor and packet processor devices. Mr. Reddy also held various management roles at Actel and ChipExpress (now ChipX).
Mr. Reddy holds a master's degree in electrical engineering from Princeton University and a bachelor's degree from the University of Southern California.
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