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Technical Papers |
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Unique 1.6 GSPS CMOS 8-bit 1.8V ADC Delivers 7.26 ENOB Past Nyquist
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Robert Taft, Chris Menkus, Maria Rosaria Tursi, Ols Hidri, Valerie Pons, and Paul McCormack
National Semiconductor
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Oct 2004
Euro DesignCon 2004 Paper |
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Enabling Terabit Backplanes Using Channel Optimization to Reduce the Need for Equalization
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Thomas Brenner and Karsten Wolff, John D'Ambrosia and Christian Koehler
Alcatel and Tyco Electronics
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Oct 2004
Euro DesignCon 2004 Paper |
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Identifying Sources of Jitter
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Johnnie Hancock
Agilent Technologies
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Oct 2004
Euro DesignCon 2004 Paper |
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Physical Design Methodology for a 0.13um System on a Chip
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Pradeep Buddharaju, Kent Goodin, and Santhosh Pillai
Parama Networks
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Oct 2004
Euro DesignCon 2004 Paper |
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Implementing High-Speed RLDRAM II Interfaces Using FPGAs
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Sanjay Charagulla and Lalitha Oruganti
Altera
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Apr 07, 2004
DesignCon East 2004 Conference Paper |
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Testing High Speed Serial IO Interfaces Based on Spectral Jitter Decomposition
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Rainer Plitschka and Bernd Laquai
Agilent Technologies
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Feb 04, 2004
DesignCon 2004 Conference Paper |
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Multi-Core Embedded Debug for Structured ASIC Systems
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Dr. Neal Stollon, Rick Leatherman, Bruce Ableidinger, and Ernie Edgar
First Silicon Solutions
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Feb 04, 2004
DesignCon 2004 Conference Paper |
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Formal Verification of Block-level Requirements
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Harry Foster, C. Norris Ip, Howard Wong-Toi, and Douglas Perry
Jasper Design Automation
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Feb 04, 2004
DesignCon 2004 Conference Paper |
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