Abhishek Roy
Freescale Semiconductor

Routing congestion has traditionally been a major bottleneck during place-and-route, timing and physical design closure in sub 90 nm designs. The aggressive targets of obtaining a competitive die-size and ever-increasing requirements of maximum device operating frequency, render place and route design closure more challenging. Moreover lesser number of interconnect mask layers in some process nodes pose stringent challenges in routing to the designer. This paper proposes a novel algorithm to alleviate congestion hot-spots by first estimating the standard cell local pin density and subsequently modifying physical attributes of identified culprit cells based on timing criticality.