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Understanding the Basics of the Wafer-Level Chip-Scale Package (WL-CSP)

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Application Note
250 KB (12 pages)
May 1, 2008
 

Maxim Integrated Products

This application note discusses Maxim's wafer-level chip-scale package (WL-CSP). Topics include: wafer construction, tape-and-reel packaging, PCB layout, and assembly and reflow. The article supplies reliability stress-test data per the IPC and JEDEC standards.

 
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