Anurag Jindal
Freescale Semiconductor

As Design-for-Test (DFT) Engineers, we are always in a quest for achieving Zero- Defect (ZD). When it comes to memories, numerous flavors of memory BIST are available which cover all possible faults in a memory. But often, proper attention is not given to the 'logic surrounding the memories' assuming that BIST or scan patterns will target the faults in this logic. As a result, we end up having an undertested surrounding logic in most of the cases and over-tested/wrongly-tested logic in few other cases.

The goal should be to achieve cent-percent and, more importantly, correct coverage for this logic. In this paper, you will learn about the different techniques applied to test this logic, their pros and cons, and the correct method of applying these so as to get correct coverage with optimum set of test vectors.