Pete McCrorie and Harish Kriplani
Cadence

As device geometries shrink and device densities increase, it has become increasingly difficult to design chips that are robust from the perspectives of timing, power, and noise. Good power integrity cannot be achieved by simply modifying power routing just prior to tapeout based on signoff analysis results. It comes as a result of paying attention to power requirements throughout the design flow—from early design conception, through implementation, all the way to signoff. This paper explains how a comprehensive power integrity solution that is integrated with design implementation and timing/SI analysis is necessary to avoid missed tapeout windows or failed silicon.