Travis Lewis et al
AMD and Mentor Graphics

With each new process technology node chip designs increase in complexity and size, and mask data prep flows require more compute resources to maintain the desired turn around time (TAT) at a low cost. Securing highly scalable processing for each element of the flow—geometry processing, resolution enhancements and optical process correction, verification and fracture—has been the focal point so far. The utilization for different flow elements depends on the operation, the data hierarchy and the device type. This paper introduces a dynamic utilization driven compute resource control system applied to large scale parallel computation environment. The paper will analyze performance metrics TAT and throughput for a production system and discuss trade-offs of different parallelization approaches in data processing regarding interaction with dynamic resource control. The study focuses on 65nm and 45nm designs.