Jay O'Donnell
Mentor Graphics

Using a current benchmark as the basis for the content, this paper describes a Questa/inFact solution with which a small engineering team was able to fully verify an SOC IP module design in less time and with fewer resources than with their current constrained random test solution.

Rather than limiting test generation to random tests, inFact used several algorithms to generate intelligent test sequences for simulation. In the head-to-head comparison, the Questa and inFact solution discovered every design error found by the current toolset, plus several more. And by synthesizing and simulating only meaningful test sequences, Questa and inFact found the design bugs earlier in the simulation process, and with fewer simulation resources.