Amjad Qureshi and John Brennan
Cadence

Verification requirements for advanced ARM processor-based system-on-chip (SoC) devices already consume a disproportionate share of engineering resources, and the trend toward growing SoC complexity threatens to compound verification challenges. To manage these concerns, design organizations are looking for an enterprise-level verification environment that encompasses block-, chip-, and system-level verification of ARM processor-based SoC designs. This article delves into SoC design challenges and explores the emergence of comprehensive verification design kits tailored to ARM processor-based devices that enable engineers to address the full range of verification requirements of these complex SoCs.